This application claims the benefit of Korean Application No. 2000-60257, filed Oct. 13, 2000, in the Korean Industrial Property Office, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving an alternating current (AC) type triode surface-discharge plasma display panel by applying an AND logic driving method to an address-display separation driving method.
2. Description of the Related Art
The structures of plasma display panels are largely classified into a counter-discharge structure and a surface-discharge structure depending on the arrangement of discharging electrodes. In addition, methods of driving a plasma display panel are classified into a direct current (DC) driving method and an AC driving method depending on whether the polarity of a driving voltage changes or not.
Referring to FIGS. 1A and 1B, discharge spaces 16 are formed between front glass substrates 10 and 1, and rear- glass substrates 20 and 2 in a plasma display panel of DC type counter-discharge structure and a plasma display panel of AC type surface-discharge structure, respectively. Referring to FIG. 1A, in the DC type plasma display panel, a scan electrode 18 and an address electrode 11 are directly exposed to the discharge space 16. Referring to FIG. 1B, in the AC type plasma display panel, display electrodes 3 to perform display are disposed within a dielectric layer 5 so that the display electrodes 3 are electrically separated from the discharge space 16. Here, display is performed by a well-known wall-charge effect. For example, in discharge cells where discharge is provoked between an address electrode 8 and a scan electrode 3a, wall charges are formed around the address electrode 8 and the scan electrode 3a. Thereafter, a voltage lower than a discharge triggering voltage is applied between the line of the scan electrode 3a and the line of a common electrode 3b so that display can be performed only in discharge cells where wall charges are formed around the scan electrode 3a. Reference numeral 5xe2x80x2 denotes a dielectric layer covering the address electrode 8.
Referring to FIG. 2, the address electrode lines 8, the dielectric layers 5 and 5xe2x80x2, the X-Y electrode lines 3, barriers 6 and a magnesium monoxide (MgO) layer 9 as a protective layer are provided between the front glass substrate 1 and the rear glass substrate 2 in a conventional AC type triode surface-discharge plasma display panel. Reference numeral 4 denotes a metal electrode line to increase the conductivity of each X-Y electrode line 3. Each X-Y electrode line 3 includes a scan electrode 3a and a common electrode 3b as shown in FIG. 1B.
The parallel address electrode lines 8 are formed on a top surface of the rear glass substrate 2. The rear dielectric layer 5xe2x80x2 is deposited on the entire surface of the rear glass substrate 2 having the address electrode lines 8. The barriers 6 are formed on the surface of the rear dielectric layer 5xe2x80x2 such that the barriers 6 are parallel to the address electrode lines 8. The barriers 6 define the discharge areas of discharge cells and prevent optical crosstalk between adjacent discharge cells. A phosphor layer 7 is formed between adjacent pairs of the barriers 6. The phosphor layer 7 generates light having a color (red, green, or blue) corresponding to ultraviolet rays generated due to the discharge of each discharge cell.
The X-Y electrode lines 3 are formed on a bottom surface of the front glass substrate 1 in a direction perpendicular to a direction of the address electrode lines 8. The discharge cells are defined at intersections of the X-Y electrode lines 3 and the address electrode lines 8. The front dielectric layer 5 is deposited on the entire bottom surface of the front glass substrate 1 having the X-Y electrode lines 3. The MgO layer 9, which protects a display panel from an intensive electric field, is deposited on the entire surface of the front dielectric layer 5. Gas (not shown) used to form a plasma is sealed in the discharge space 16.
FIG. 3 illustrates a typical address-display separation driving method for the AC type triode surface-discharge plasma display panel of FIG. 2. FIG. 4 illustrates the interactions between the X-Y electrode lines 3 and the address electrode lines 8 used to perform in the driving method of FIG. 3 in the plasma display panel of FIG. 2. Referring to FIGS. 3 and 4, a unit frame (i.e., a unit television field) is divided into 6 sub-fields SF1 through SF6 to realize time division gray-scale display. In addition, each of the sub-fields SF1 through SF6 is divided into corresponding address periods A1 through A6 and sustain periods S1 through S6. During each of the address periods A1 through A6, a display data signal is applied to address electrode lines AR1, . . . , AB5, and simultaneously, corresponding scan pulses are sequentially applied to Y electrode lines Y1 through Y16. Accordingly, when the display data signal of a high level is applied while scan pulses are being applied, wall charges are formed in the corresponding discharge cells due to the address discharge. In the discharge cells other than the corresponding discharge cells, wall charges are not formed.
During each of the sustain periods S1 through S6, a display pulse is alternately applied to all the Y electrode lines Y1 through Y16 and all the X electrode lines X1 through X16 so that a display is performed in the discharge cells having the wall charges. Therefore, the luminance of a plasma display panel is proportional to the time of the sustain periods S1 through S6 in a unit television field.
Here, the sustain period S1 of the first sub-field SF1 is set to a time 1T corresponding to 20. The sustain period S2 of the second sub-field SF2 is set to a time 2T corresponding to 21. The sustain period S3 of the third sub-field SF3 is set to a time 4T corresponding to 22. The The sustain period S4 of the fourth sub-field SF4 is set to a time 8T corresponding to 23. The sustain period S5 of the fifth sub-field SF5 is set to a time 16T corresponding to 24. The sustain period S6 of the sixth sub-field SF6 is set to a time 32T corresponding to 25. Consequently, among the 6 sub-fields SF1 through SF6, a sub-field to be displayed can be appropriately selected so that gray-scale display can be performed.
FIGS. 5A through 5E illustrate the driving signals in the unit sub-field SF1 according to the address-display separation driving method of FIG. 3. Here, it is assumed that a plasma display panel to which the driving method of FIG. 5 is applied has n red (R) address electrode lines, n green (G) address electrode lines, n blue (B) address electrode lines, and 480 pairs of the X and Y electrode lines. In FIGS. 5A through 5E, reference character SAR1, . . . , ABn denotes a driving signal applied to the address electrode lines AR1, AG1, . . . , AGn, ABn, reference character SX1, . . . ,X480 denotes a driving signal applied to the corresponding X electrode lines X1 through X480, and reference character SY1, . . . ,Y480 denotes a driving signal applied to the corresponding Y electrode lines Y1 through Y480. Referring to FIGS. 5A through 5E, the address period A1 in the unit sub-field SF1 is divided into reset periods A11, A12 and A13 and a main address period A14.
During the sustain period S1, a display pulse 25 is alternately applied to all the Y electrode lines Y1 through Y480 and all the X electrode lines X1 through X480 so that the display is performed in the discharge cells having the wall charges formed during the corresponding address period A1. When a final pulse is applied to the X electrode lines X1 through X480 during the sustain period S1, electrons are formed around X electrodes of the selected discharge cells for display, and positive charges are formed around the Y electrodes thereof. Accordingly, during the first reset period of the next subfield, a pulse 22a having a lower voltage and larger width than the display pulse 25 is applied to the X electrode lines X1 through X480 to perform a discharge to primarily remove the wall charges. In addition, during the second reset period A12, a pulse 23 having the same voltage as and a smaller width than the display pulse 25 is applied to all the Y electrode lines Y1 through Y480 so that discharging for secondarily removing the remaining wall charges is performed. During the third reset period A13, a pulse 22b having a lower voltage and a larger width than the display pulse 25 is applied to the X electrode lines X1 through X480 to perform a discharge to finally remove the wall charges. Consequently, all the wall charges can be removed from the discharge space, and space charges can be uniformly distributed during reset periods A11, A12, and A13.
During the main address period A14, a display data signal is applied to the address electrode lines AR1, AG1, . . . , AGn, ABn, and simultaneously, a scan pulse 24 is sequentially applied to the Y electrode lines Y1 through Y480. For the display data signal applied to each of the address electrode lines AR1, AG1, . . . , AGn, ABn, a positive polarity voltage Va is applied when selecting a discharge cell, bul. otherwise, a ground voltage (i.e., 0 V) is applied. A bias voltage of a positive polarity is applied to the Y electrode lines Y1 through Y480 while a scan is not performed, and the scan pulse 24 of 0 V is applied thereto while a scan is being performed. Accordingly, when the display data signal is applied while the scan pulse 24 of 0 V is being applied, wall charges are formed in the corresponding discharge cells due to address discharge, but are not formed in the other discharge cells. Here, to realize more accurate and efficient address discharging, a bias voltage lower than that of the display data signal is applied to the X electrode lines X1 through X480.
According to such a typical address-display separation driving method, there are 480 Y driving devices to drive the Y electrode lines Y1 through Y480. For example, when driving a plasma display panel having 480 pairs of the X and Y electrode lines, a single X driving device and 480 Y driving devices are required. As many driving devices are required in proportion to the vertical resolution of a plasma display apparatus, the power consumption and manufacturing cost of the plasma display apparatus increase.
To solve the above and other problems, it is an object of the present invention to provide a method of driving a plasma display panel through which an address voltage applied to address electrode lines and a sustain voltage applied to sustain electrode lines can be reduced when the plasma display panel is driven by an address-display separation driving method and an AND logic driving method.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Accordingly, to achieve the above and other objects of the invention, a method of driving a plasma display panel according to an embodiment of the invention includes, for the plasma display panel having front and rear substrates disposed opposite each other, parallel X and Y electrode lines formed between the front and rear substrates, and address electrode lines having a direction perpendicular to a direction of the X and Y electrode lines to define discharge cells at intersections of the X and Y electrode lines and the address electrode lines, where the X electrode lines are combined in X groups, the Y electrode lines are combined in Y groups, adjacent pairs of the X and Y electrode lines belong to different pairs of the X and Y groups, the X electrode lines are commonly interconnected in units of the X groups, and the Y electrode lines are commonly interconnected in units of Y groups, the method includes a reset operation, a first scan operation, a first address operation, a repetition operation, and a sustain operation.
According to an aspect of the present invention, in the reset operation, wall charges formed in a previous sub-field are erased, in the first scan operation, a Y scan pulse of a first polarity is applied to the Y electrode lines of a first pair of the X and Y groups including a first pair of the X and Y electrode lines, and simultaneously, an X scan pulse of a second polarity opposite to the first polarity is applied to the X electrode lines thereof so that wall charges of the second polarity are formed around the Y electrodes on the first pair of the X and Y electrode lines.
According to another aspect of the present invention, in the first address operation, a display data signal corresponding to the first pair of the X and Y electrode lines is applied to all the address electrode lines, and simultaneously, a bias voltage of the first polarity is applied to the Y electrode lines of the first pair of the X and Y groups, and a bias voltage of the second polarity is applied to the X electrode lines thereof so that the wall charges that have been formed at discharge cells of the first pair of X and Y electrode lines are erased, which are not to be displayed and wall charges of the second polarity are additionally formed around the Y electrodes of discharge cells which are to be displayed on the first pair of X and Y electrode lines.
According to a further aspect of the present invention, in the repetition operation, the first scan operation and the address operation are performed on the sequential remaining pairs of X and Y electrode lines.
According to a still further aspect of the present invention, in the sustain operation, an operation of applying a sustain pulse of the second polarity to all the Y electrode lines and then applying a sustain pulse of the second polarity to all the X electrode lines is repeatedly performed for a time corresponding to the gray-scale of a current sub-field.
In a method of driving such a plasma display panel according to another embodiment of the present invention, wall charges of the second polarity are additionally formed around the Y electrodes of discharge cells which are displayed on the first pair of X and Y electrode lines in the first address operation, and the first address operation is sequentially performed on the remaining pairs of X and Y electrode lines in the repetition operation such that an address voltage applied to the address electrode lines and a sustain voltage applied to sustain electrode lines can be set to low levels.